10 digits of e is easy-peasy due to the repeating structure: 2.7 1828 1828.

Floating point significands have a structure of (1 ± ∆) and (1 ± ∆)^N ≈ 1 ± N*∆. From that we can estimate the least number of bits or digits required to achieve D decimal places of accuracy. But the upper bound on the number of required bits or digits to get D decimal places is actually unbounded in the general case due to the non-zero chance of getting a round-up/round-down ambiguity in the deeper digits.

It seems that induced errors (caused by rounding of products aXb) is uniformly distributed in interval [-u/2, u/2] where u is machine precision. Is that reasonable?

Approximately, yes, but empirically and theoretically, no.

1. Empirical non-uniformity: Benford's Law would predict a slight bias in the distribution, especially if one is looking at low precision multiplication.

2. Theoretical non-uniformity: The induced errors sometimes occur on [-u,+u/2], [-u/2,+u] for cases where a*b is on the cusp of a change in exponent. The induced errors can be stranger in cases related to underflow and overflow. (Assuming we're talking about IEEE-style floating point with a fixed division of bits between significand and exponent)

3. Dangerous assumptions about inputs: For a & b that are IID and "smoothly" distributed, uniformity might be fine. But if a & b are drawn from the set of powers of two or any set with a preponderance of powers of two, the chance of induced error of zero would be higher than expected. And what if the upstream process that produces a and b actually has b = 1/a? This feels like one of those software contract issues in which the code that does stuff with the induced error on low precision a*b uses some non-trivial assumptions about the nature of a and b that the user of the software needs to understand.